On the Acceleration of Test Generation Algorithms
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[1] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[2] Thomas W. Williams,et al. A logic design structure for LSI testability , 1977, DAC '77.
[3] F. F. Sellers,et al. Analyzing Errors with the Boolean Difference , 1968, IEEE Transactions on Computers.
[4] Füsun Özgüner,et al. 9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits , 1978, IEEE Transactions on Computers.
[5] Ernst G. Ulrich,et al. Concurrent simulation of nearly identical digital networks , 1974, Computer.
[6] J. Paul Roth,et al. Diagnosis of automata failures: a calculus and a method , 1966 .
[7] Prabhakar Goel,et al. PODEM-X: An Automatic Test Generation System for VLSI Logic Structures , 1981, 18th Design Automation Conference.
[8] L. H. Goldstein,et al. Controllability/observability analysis of digital circuits , 1978 .
[9] Toshihiro Arima,et al. Test generation systems in Japan , 1975, DAC '75.