Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies
暂无分享,去创建一个
[1] D. R. Fulkerson,et al. Maximal Flow Through a Network , 1956 .
[2] Jason Baumgartner,et al. Exploiting suspected redundancy without proving it , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[3] Sela Mador-Haim,et al. Input Elimination and Abstraction in Model Checking , 1998, FMCAD.
[4] C.A.J. van Eijk. Sequential equivalence checking without state space traversal , 1998, Proceedings Design, Automation and Test in Europe.
[5] Jason Baumgartner,et al. Scalable Automated Verification via Expert-System Guided Transformations , 2004, FMCAD.
[6] Daniel Kroening,et al. A SAT-based algorithm for reparameterization in symbolic simulation , 2004, Proceedings. 41st Design Automation Conference, 2004..
[7] Ganesh Gopalakrishnan,et al. Efficient symbolic simulation-based verification using the parametric form of Boolean expressions , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Zijiang Yang,et al. Iterative Abstraction using SAT-based BMC with Proof Analysis , 2003, ICCAD 2003.
[9] Fabio Somenzi,et al. Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis , 2002, TACAS.
[10] Helmut Veith,et al. Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis , 2002, FMCAD.
[11] Kunle Olukotun,et al. Efficient state representation for symbolic simulation , 2002, DAC '02.
[12] C. A. J. van Eijk,et al. Sequential equivalence checking without state space traversal , 1998, DATE.
[13] In-Ho Moon,et al. Simplifying Circuits for Formal Verification Using Parametric Representation , 2002, FMCAD.
[14] Ofer Strichman,et al. SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques , 2002, CAV.
[15] Charles E. Leiserson,et al. Retiming synchronous circuitry , 1988, Algorithmica.
[16] Jiang Long,et al. Formal property verification by abstraction refinement with formal, simulation and hybrid engines , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[17] Kathi Fisler,et al. Bisimulation and Model Checking , 1999, CHARME.
[18] Adnan Aziz,et al. An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists , 2003, Formal Methods Syst. Des..
[19] Carl-Johan H. Seger,et al. Parametric Representations of Boolean Constraints. , 1999, DAC 1999.
[20] Fabio Somenzi,et al. Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States , 2004, FMCAD.
[21] Malay K. Ganai,et al. Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[22] Orna Grumberg,et al. Model checking and modular verification , 1994, TOPL.
[23] Rajeev Alur,et al. A Temporal Logic of Nested Calls and Returns , 2004, TACAS.
[24] V. Bertacco,et al. Efficient state representation for symbolic simulation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[25] Carl-Johan H. Seger,et al. Formal verification using parametric representations of Boolean constraints , 1999, DAC '99.
[26] Jason Baumgartner,et al. Transformation-Based Verification Using Generalized Retiming , 2001, CAV.
[27] Jacob A. Abraham,et al. Property Checking via Structural Analysis , 2002, CAV.
[28] George J. Milne,et al. Correct Hardware Design and Verification Methods , 2003, Lecture Notes in Computer Science.
[29] Thomas R. Shiple,et al. Building Circuits from Relations , 2000, CAV.