CMOS Metrics and Model Evaluation
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[1] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .
[2] C. Auth,et al. 45nm High-k + metal gate strain-enhanced transistors , 2008, 2008 Symposium on VLSI Technology.
[3] Dmitri E. Nikonov,et al. Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking , 2013, Proceedings of the IEEE.
[4] G. G. Shahidi. SOI technology for the GHz era , 2002, IBM J. Res. Dev..
[5] Jan M. Rabaey,et al. Digital Integrated Circuits , 2003 .
[6] Manjul Bhushan,et al. Microelectronic Test Structures for CMOS Technology , 2011 .
[7] Manjul Bhushan,et al. An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability , 2007, Proceedings of the IEEE.
[8] M. B. Ketchen. Competitive advantage of SOI from dynamic threshold shifts and reduced capacitance , 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).
[9] Qiang Chen,et al. Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[10] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[11] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.
[12] S. Tyagi,et al. High performance 35nm L/sub GATE/ CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2nm gate oxide , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..