A custom-designed integrated circuit for the realization of residue number digital filters
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Results are presented on the design, layout, and fabrication of a custom-designed integrated circuit for a residue number system digital filter module. The architecture is based on a ROM-ACCUMULATOR FIR structure in which the modular arithmetic for each modulus is realized on a separate chip. The modules are designed to support error detection and fault isolation at module boundaries. Of the five chips that were fabricated and tested, all were found to be fully operational, with three operating at a maximum data-cycle frequency of approximately 1.7 MHz.
[1] W. Kenneth Jenkins,et al. The use of residue number systems in the design of finite impulse response digital filters , 1977 .
[2] W.K. Jenkins. A highly efficient residue-combinatorial architecture for digital filters , 1978, Proceedings of the IEEE.
[3] Basant R. Chawla,et al. Motis - an mos timing simulator , 1975 .
[4] W. Kenneth Jenkins,et al. The Design of Error Checkers for Self-Checking Residue Number Arithmetic , 1983, IEEE Transactions on Computers.