A Novel Charge Recycling Scheme in Power Gating Design

Power gating has become a popular technique to reduce the ever-increasing leakage power for commercial microprocessors or SoCs. The reactivation energy and delay cost weaken its performance. This paper firstly proposes a novel charge recycling scheme to reduce the transition energy and delay, and then gives its equivalent model. The experiment results show that, comparing to the traditional power gating implementation, it can achieve 19.66% reactivation energy reduction, 9.28% peak leakage reduction, and 23.36% wakeup delay reduction, at 25°C, at the cost of 2.75% area increasing. At the same time, the circuit reliability is improved since the ground bounce reduced.

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