Formal specification and analysis of digital hardware circuits in LOTOS

The thesis discusses using ISO standard formal language L OTOS (Language of Temporal Ordering Specification) for formally specifying and analysing digit al circuits. The study serves two-fold: it examines the possibility of extending applications of L OTOSoutside its traditional areas, and provides a new formalism to aid designing correct hardware. Digital circuits are usually classified into synchronous (c locked) and asynchronous (un-clocked) circuits. The thesis addresses both of them. L OTOSmodels for signals, wires, components and component connections are established, together with the behavioura l models of digital components in synchronous and asynchronous circuits. These formal models help to buil d the rigorous specifications of digital circuits, which are not only valuable documentation, but also t he bases for further analysis. The investigation of the thesis shows that L OTOS is suitable for specifying digital circuits at various leve ls of abstraction. Compared with other formalisms, it is especia lly efficient on higher level modelling. But there is also a gap between L OTOS models and real world hardware, which is the result of the dif ference between inputs and outputs of systems being abstracted way in LOTOS. The gap is bridged by introducing input receptive or input quasi-receptive spec ifications. Two analysis approaches are investigated in the thesis, nam ely formal verification and conformance testing. Verification intends to check the correctness of th e formal model of a circuit, it is exhaustive and can ensure the correctness of the model being checked. While testing is applied to a physical product or a formal or informal model, it can never be exhaustive but are v ery useful when a formal model is difficult to build. Current LOTOSverification techniques support the three common verificati on tasks, i.e. requirements capture, implementation verification and design verificati on. In this thesis, model checking is used to fulfill the tasks. It is found that verification of synchronou s circuits is relatively straightforward since LOTOS tools can be directly used. For verifying asynchronous circ uits, two conformance relations are defined to take the different roles of inputs and outputs into account. Compared with other hardware verification approaches, the approach presented in this the sis as the advantage of finding bugs at early stages of development, because L OTOS can be used in higher level modelling. Moreover, L OTOS is supported by various verification techniques, which are com ple entary to each others and give more chances to detect design faults. The thesis explores a new direction of applying formal metho ds to digital circuit design. The basic idea is to combine formal methods with traditional validati on approaches. L OTOSconformance testing theory is employed to generate test cases from higher level f ormal specifications. The test cases are then applied to commercial VHDL (VHSIC Hardware Description Lan guage) simulators to simulate lower level circuit designs. Case studies reveals that the approa ch is very promising. For example, it can detect bugs which cannot be captured by examining a formal model. Timing characteristics are important factors in digital de sign. To be able to specify and analyse timed circuits, ET-LOTOS is exploited. Two important timing characteristics in digi tal circuits, namely delays and timing constraints are identified. Timed specifications f digital circuits are the composition of these timing characteristics and functionality. Based on the for mal specifications, rigorous analysis can be applied. The method is valuable in discovering subtle desig n bugs related to timing, such as hazard, race conditions, and can also be used for analysing speed perform ance of digital circuits.