Calibration study of dual-band Weaver-Hartley receiver architecture

This paper presents a calibration study of dual-band image rejection receiver based on combined Weaver-Hartley architecture, with improved image rejection of first and second image signals. The system implementation is based on dual-band WLAN 802.11 a/g. When the desired signal is at 5.7-GHz band, the 2.4-GHz band becomes the first image signal and vice versa. The output IF frequency is at 30-MHz. The detection of the gain and phase mismatches is based on modeling, extraction of related error signals and correcting them in closed loop. Moreover, we demonstrate an open loop technique to reach the phase and gain correction signals. The correction signals can be digitally stored and applied as digital trimming control on the LO signals. Simulation showed close to 60dB of image rejection ratio for the first image signal. Second image signal is rejected by a 4-section poly-phase filter.

[1]  M.A.I. Elmala,et al.  Automatic mismatches calibration in Hartley image-reject receiver , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[2]  B. Razavi,et al.  A 2 GHz CMOS image-reject receiver with sign-sign LMS calibration , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  Chinchun Meng,et al.  2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver–Hartley Image-Rejection Techniques , 2009 .

[4]  M.A.I. Elmala,et al.  Calibration of phase and gain mismatches in Weaver image-reject receiver , 2004, IEEE Journal of Solid-State Circuits.

[5]  Jacques C. Rudell,et al.  A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications , 1997, IEEE J. Solid State Circuits.

[6]  G. Chien,et al.  A 1.9 GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[7]  B. Razavi,et al.  A 900 MHz/1.8 GHz CMOS receiver for dual band applications , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[8]  Michiel Steyaert,et al.  A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology , 1995, IEEE J. Solid State Circuits.

[9]  A. Abidi,et al.  A 900 MHz dual conversion low-IF GSM receiver in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[10]  Asad A. Abidi,et al.  A 900 MHz dual conversion low-IF GSM receiver in 0.35 μm CMOS , 2001 .

[11]  A. Abidi,et al.  A 2 . 4-GHz Low-IF Receiver for Wideband WLAN in 0 . 6-m CMOS — Architecture and Front-End , 2000 .

[12]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[13]  A.A. Abidi,et al.  A 2.4-GHz low-IF receiver for wideband WLAN in 6-/spl mu/m CMOS-architecture and front-end , 2000, IEEE Journal of Solid-State Circuits.