Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
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Diederik Verkest | Anabela Veloso | Aaron Thean | Philippe Roussel | Piet Wambacq | Julien Ryckaert | Praveen Raghavan | Nadine Collaert | Ivan Ciofi | Abdelkarim Mercha | Trong Huynh Bao | Jürgen Bömmels | Zsolt Tokei | Rogier Baert | S. Demuynck | Dmitry Yakimets
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