A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS

A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100–200 <formula formulatype="inline"><tex Notation="TeX">${\rm mV}_{\rm ppd}$</tex></formula> using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65 nm CMOS process, the transceiver achieves 4.8–8 Gb/s at 0.47–0.66 pJ/b energy efficiency for <formula formulatype="inline"><tex Notation="TeX">${\rm V}_{\rm DD}=0.6$</tex></formula>–0.8 V.

[1]  Ting Wu,et al.  A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface , 2009, IEEE Journal of Solid-State Circuits.

[2]  Thomas Toifl,et al.  A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[3]  Eisse Mensink,et al.  A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Kari Halonen,et al.  Analysis and Design of Passive Polyphase Filters , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Goichi Ono,et al.  A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process , 2010, IEEE Journal of Solid-State Circuits.

[6]  Brian Ellis.  The Design of CMOS Radio-Frequency Integrated Circuits , 2004 .

[7]  Samuel Palermo,et al.  A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Thomas Toifl,et al.  A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology , 2012, 2012 IEEE International Solid-State Circuits Conference.

[9]  Goichi Ono,et al.  A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[10]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[11]  R. Mooney,et al.  A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[12]  James E. Jaussi,et al.  A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS , 2010, ISSCC.

[13]  M. Horowitz,et al.  A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.

[14]  Thomas Toifl,et al.  A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology , 2012, IEEE Journal of Solid-State Circuits.

[15]  Naveen Verma,et al.  Technologies for Ultradynamic Voltage Scaling , 2010, Proceedings of the IEEE.

[16]  Samuel Palermo,et al.  0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking , 2012, IEEE Journal of Solid-State Circuits.

[17]  Vladimir Stojanovic,et al.  Digital link pre-emphasis with dynamic driver impedance modulation , 2010, IEEE Custom Integrated Circuits Conference 2010.

[18]  M. Horowitz,et al.  - A 0 . 8pm CMOS 2 . 5 Gb / s Oversampling Receiver and Transmitter for Serial Links , 1999 .

[19]  Patrick Chiang,et al.  A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[20]  Bryan Casper,et al.  A 47$\,\times\,$ 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[21]  Samuel Palermo,et al.  A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[22]  Jaeha Kim,et al.  Adaptive supply serial links with sub-1 V operation and per-pin clock recovery , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[23]  Lei Luo,et al.  A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[24]  Bryan Casper,et al.  Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  James E. Jaussi,et al.  A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[26]  Chih-Kong Ken Yang,et al.  A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links , 1996 .

[27]  Amr Elshazly,et al.  A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[28]  Masum Hossain,et al.  7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[29]  Thomas Toifl,et al.  A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[30]  C. Menolfi,et al.  A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.