Mapping Graphs onto a Partially Reconfigurable Architecture

As we search for a mapping that will avoid the routing of data, our interest in this paper was to characterize the graphs for which there exits a topological mapping onto an RTRN and to simulate the behaviour of an application running onto this machine according to this mapping. After we have determined the kind of graph which is assignable we realize a software tool which simulates the execution of the tasks and which gives a graphical interpretation of the mapping.