High-performance and low-voltage challenges for sub-45nm microprocessor circuits

Increasingly aggravated challenges in CMOS technology scaling beyond the 45nm node has resulted in several new design paradigm shifts necessary for high-performance and low-power microprocessors. This paper discusses some of the key technology challenges and the associated design paradigm shifts. High-performance and low-voltage energy-efficient circuit techniques to combat (i) increasing switching and active leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are presented.