Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

In this paper, we introduce a statistical approach for studying a special class of nonlinear dynamical systems such as ADPLLs and ADPLL networks, where the process driving the adjustment of the DCO frequency can be seen as ∑Δ modulation. We showed that, by applying the Frobenius-Perron operator to the governing equation, it is possible to find the invariant probability density which is valid for dynamically changing input of ∑Δ modulator. By using this, we show that the average behaviour of the corresponding complex system can be dramatically simplified and studied analytically.

[1]  A. Demir.  Phase noise and timing jitter in oscillators with colored-noise sources , 2002 .

[2]  Orla Feely,et al.  Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Timo Koski,et al.  Statistics of the binary quantizer error in single-loop sigma-delta modulation with white Gaussian input , 1995, IEEE Trans. Inf. Theory.

[4]  Pieter Rombouts,et al.  Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Olivier Billoint,et al.  Distributed clock generator for synchronous SoC using ADPLL network , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[6]  Orla Feely,et al.  Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks , 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[7]  A. Demir,et al.  Phase noise in oscillators: a unifying theory and numerical methods for characterization , 2000 .

[8]  Olivier Billoint,et al.  A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs , 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

[9]  Qi Wang,et al.  The Implementation and Analysis of a New Self-Sampling Pi Control All Digital Phase-Locked Loop , 2006, 2006 International Conference on Machine Learning and Cybernetics.

[10]  Giovanni Marucci,et al.  Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Dimitri Galayko,et al.  A reconfigurable distributed architecture for clock generation in large many-core SoC , 2014, 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

[12]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[13]  Abhishek Agrawal,et al.  2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[14]  Qun Jane Gu,et al.  Analysis and Design of Bang-Bang PD-Based Phase Noise Filter , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Poras T. Balsara,et al.  Time-Domain Modeling of an RF All-Digital PLL , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  Jae-Yong Ihm,et al.  Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems , 2013, IEEE Trans. Circuits Syst. II Express Briefs.

[17]  Robert M. Gray,et al.  Oversampled Sigma-Delta Modulation , 1987, IEEE Trans. Commun..

[18]  Fernando Corinto,et al.  Phase Space Decomposition for Phase Noise and Synchronization Analysis of Planar Nonlinear Oscillators , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[19]  Nicola Da Dalt.  A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs , 2005, IEEE Trans. Circuits Syst. I Regul. Pap..

[20]  Giovanni Marucci,et al.  Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Orla Feely,et al.  Driven interval shift dynamics in sigma-delta modulators and phase-locked loops , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  A.P. Chandrakasan,et al.  Active GHz clock network using distributed PLLs , 2000, IEEE Journal of Solid-State Circuits.

[23]  Gill A. Pratt,et al.  Distributed Synchronous Clocking , 1995, IEEE Trans. Parallel Distributed Syst..

[24]  Jérôme Juillard,et al.  A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops , 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

[25]  François Chapeau-Blondeau,et al.  Stochastic resonance for an optimal detector with phase noise , 2003, Signal Process..

[26]  Orla Feely,et al.  Semianalytical model for high speed analysis of all-digital PLL clock-generating networks , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[27]  Orla Feely,et al.  Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[28]  Orla Feely,et al.  Limit cycles in bang-bang phase-locked loops , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[29]  Eby G. Friedman,et al.  Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.

[30]  Ching-Yuan Yang,et al.  A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.