ULTRA-HIGH SPEED MULTIPLEXER/DEMULTIPLEXER ARCHITECTURES

This paper describes two circuit architectures for ultra-high speed digital multiplexers and demultiplexers. The first, Type-I, is fully synchronous and uses a system clock that matches the maximum data rate. Circuits of this type can operate at a data rate equal to the maximum operating speed of a simple digital divider. A simpler and much more powerful architecture is proposed, Type-II, that operates using a half-frequency system clock at data rates up to twice the maximum clock speed of a simple digital divider. Basic building blocks and high speed design techniques are reviewed.