The effect of clock jitter on the performance of continuous-time delta-sigma ADC for GNSS signals
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Next generation Global Navigation Satellite
System (GNSS) receivers will operate in multiple
navigation bands. An efficient way to achieve this with
lower power and cost is to employ BandPass Sampling
(BPS); nevertheless, the sampling operation injects large
amounts of jitter noise, which degrades the performance
of the receiver. Continuous–Time (CT) Delta–Sigma
(ΔΣ) modulators are capable of suppressing this noise
but the impact of clock jitter at the output of the Digital–
to–Analog Converter (DAC) in the feedback path of the
modulator should be taken into account. This paper
presents an analytical approach for describing clock
jitter in GNSS receivers when a CT–ΔΣ modulator is
utilized for Analog–to–Digital Conversion (ADC). The
validity of the presented approach is verified through
time–domain simulations using a behavioural model of
the fourth–order CT–ΔΣ modulator with 1–bit NRZ
DAC feedback pulse.