Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

[1]  Kumaki Takeshi,et al.  Super parallel SIMD processor with CAM based high-speed pattern matching capability , 2006 .

[2]  Gyohten Takayuki,et al.  A super parallel SIMD processor with Time/Space conversion Bus Bridge on the Matrix Architecture , 2006 .

[3]  K. Dosaka,et al.  A 40GOPS 250mW massively parallel processor based on matrix architecture , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[4]  Hans Jürgen Mattausch,et al.  Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory , 2007, IEICE Trans. Inf. Syst..

[5]  Hans Jürgen Mattausch,et al.  A Scalable Massively Parallel Processor for Real-Time Image Processing , 2011, IEEE J. Solid State Circuits.

[6]  Hans Jürgen Mattausch,et al.  Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor , 2008, IEICE Trans. Electron..

[7]  Shorin Kyo,et al.  Media Processing LSI Architectures for Automotives - Challenges and Future Trends - , 2007, IEICE Trans. Electron..

[8]  Elaine B. Barker,et al.  SP 800-57. Recommendation for Key Management, Part 1: General (revised) , 2007 .

[9]  Hans Jürgen Mattausch,et al.  Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor , 2007, IEICE Trans. Inf. Syst..

[10]  Hideharu Amano,et al.  A Survey on Dynamically Reconfigurable Processors , 2006, IEICE Trans. Commun..

[11]  Hans Jürgen Mattausch,et al.  Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer , 2007, IEICE Trans. Inf. Syst..

[12]  William E. Burr,et al.  Recommendation for Key Management Part 3: Application-Specific Key Management Guidance , 2009 .