Distortion Minimization for Packaging Level Interconnects
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[1] Masanori Hashimoto,et al. Performance limitation of on-chip global interconnects for high-speed signaling , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).
[2] M. Hashimoto,et al. Performance prediction of on-chip high-throughput global signaling , 2005, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005..
[3] M. Hashimoto,et al. On-chip global signaling by wave pipelining , 2004, Electrical Performance of Electronic Packaging - 2004.
[4] Masanori Hashimoto,et al. Design guideline for resistive termination of on-chip high-speed interconnects , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[5] G. Ponchak,et al. Characterization of liquid crystal polymer (LCP) material and transmission lines on LCP substrates from 30 to 110 GHz , 2004, IEEE Transactions on Microwave Theory and Techniques.
[6] Michael P. Flynn,et al. Global signaling over lossy transmission lines , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[7] Rui Shi,et al. Surfliner: a distortionless electrical signaling scheme for speed of light on-chip communications , 2005, 2005 International Conference on Computer Design.
[8] Howard W. Johnson,et al. High Speed Signal Propagation: Advanced Black Magic , 2003 .
[9] Eric D. Perfecto,et al. Thin-film multichip module packages for high-end IBM servers , 1998, IBM J. Res. Dev..