A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

[1]  Erik Jan Marinissen,et al.  Optimization Methods for Post-Bond Testing of 3D Stacked ICs , 2012, J. Electron. Test..

[2]  Janet Wu,et al.  Testing of Vega2, a chip multi-processor with spare processors. , 2007, 2007 IEEE International Test Conference.

[3]  Amitava Majumdar,et al.  A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors , 2002, Proceedings. International Test Conference.

[4]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Marcelo Lubaszewski,et al.  Reliability, Availability and Serviceability of Networks-on-Chip , 2011 .

[6]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[7]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[8]  Dong Xiang,et al.  A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing , 2013, 2013 22nd Asian Test Symposium.

[9]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[10]  Jing Wang,et al.  Test access mechanism for multiple identical cores , 2008, 2009 International Test Conference.

[11]  Francisco da Silva,et al.  The Core Test Wrapper Handbook , 2006 .

[12]  Qiang Xu,et al.  On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Krishnendu Chakrabarty,et al.  Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs , 2014, IEEE Transactions on Computers.

[14]  Yervant Zorian,et al.  Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[15]  Alexandre M. Amory,et al.  A scalable test strategy for network-on-chip routers , 2005, IEEE International Conference on Test, 2005..

[16]  Sungho Kang,et al.  A novel test access mechanism for parallel testing of multi-core system , 2014, IEICE Electron. Express.

[17]  Luca Benini,et al.  Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Takieddine SBIAI,et al.  NoC Dynamically Reconfigurable as TAM , 2012, 2012 IEEE 21st Asian Test Symposium.

[19]  W. Arden.  The International Technology Roadmap for Semiconductors—Perspectives and challenges for the next 15 years , 2002 .

[20]  Reza Nourmandi-Pour,et al.  A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC , 2013, Microelectron. J..