Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS PLL

Significant increase in design cycle time is caused by the design and optimization complexity of Analog/MixedSignal System-on-a-Chip (AMS-SoC) components as the technology moves deeper into the nanoscale domain. In this paper, a two-tier design methodology is proposed that greatly reduces design cycle time by combining accurate polynomial metamodeling and intelligent optimization. In this methodology, the parasitic-aware netlist description of an AMS-SoC component is converted into an accurate metamodel (a mathematical function or algorithm) which minimizes the time for design space exploration. Bee Colony Optimization (BCO) is subsequently used for optimization of the nano-CMOS AMS circuit. Five distinct metamodels with 21 parameters each are created for corresponding Figures of Merit (FoMs) to perform AMS-SoC component design space exploration. For a specific case study, a 180nm LC Voltage Controlled Oscillator (LC-VCO) based Phase-Locked Loop (PLL) frequency generator circuit is used this paper. The proposed optimization achieved approximately 90% power and 52% jitter reduction in comparison to the baseline design while maintaining the locking time of the PLL system. In comparison to an exhaustive simulation based design optimization approach, the proposed design flow can be up to 10 times faster and hence has potential to greatly reduce design effort and chip cost.