One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing

Approximate Computing (AC) is a design paradigm that makes use of the error tolerance inherited by many applications. The goal of AC is to trade off accuracy for performance in terms of computation time, energy consumption and/or hardware complexity.In the field of circuit design for AC, error-metrics are used to express the degree of approximation. Evaluating these error-metrics is a key challenge. Several approaches exist, however, to this day not all relevant metrics can be evaluated with formal methods. Recently, Symbolic Computer Algebra (SCA) has been used to evaluate error-metrics during approximate hardware generation. In this paper, we generalize the idea to use SCA and propose a methodology which is suitable for formal evaluation of all established error-metrics. This approach can be divided into three stages: 1) Determine the remainder of the AC circuit wrt. the specification using SCA, 2) build an Algebraic Decision Diagram (ADD) to represent the remainder and 3) evaluate each error-metric by a tailored ADD traversal algorithm. In the experiments, we apply our algorithms to a large and well-known benchmark set.

[1]  Rolf Drechsler,et al.  Formal verification of integer multipliers by combining Gröbner basis with logic reduction , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Enrico Macii,et al.  Algebric Decision Diagrams and Their Applications , 1997, ICCAD '93.

[3]  Kaushik Roy,et al.  MACACO: Modeling and analysis of circuits for approximate computing , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[4]  Alan Mishchenko,et al.  Scalable and scalably-verifiable sequential synthesis , 2008, ICCAD 2008.

[5]  Rolf Drechsler,et al.  Design Automation Techniques for Approximation Circuits: Verification, Synthesis and Test , 2018 .

[6]  Lukás Sekanina,et al.  Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[7]  Rolf Drechsler,et al.  BDD minimization for approximate computing , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[8]  Lukás Sekanina,et al.  EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[9]  Farimah Farahmandi,et al.  Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction , 2015, Microprocess. Microsystems.

[10]  Rolf Drechsler,et al.  Towards Reversed Approximate Hardware Design , 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

[11]  Rolf Drechsler,et al.  Approximate hardware generation using symbolic computer algebra employing grobner basis , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Rolf Drechsler,et al.  PolyCleaner: Clean your Polynomials before Backward Rewriting to verify Million-gate Multipliers , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[13]  Fabio Somenzi,et al.  CUDD: CU Decision Diagram Package Release 2.2.0 , 1998 .

[14]  Lukás Sekanina,et al.  ADAC: Automated Design of Approximate Circuits , 2018, CAV.

[15]  Rolf Drechsler,et al.  Precise error determination of approximated components in sequential circuits with model checking , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).