A new framework of design rules for compaction of VLSI layouts
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[1] Hiroyuki Watanabe,et al. Graph-Optimization Techniques for IC Layout and Compaction , 1983, 20th Design Automation Conference Proceedings.
[2] Yuh-Zen Liao,et al. PSI: A Symbolic Layout System , 1984, IBM J. Res. Dev..
[3] P. Smith,et al. The VIVID system approach to technology independence: the matster technology file system , 1985, DAC 1985.
[4] M. Y. Hsueh,et al. Symbolic layout and compaction of integrated circuits , 1980 .
[5] Stephen D. Posluszny. SLS: An Advanced Symbolic Layout System for Bipolar and FET Design , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Chak-Kuen Wong,et al. An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints , 1983, 20th Design Automation Conference Proceedings.
[7] Derick Wood,et al. An Optimal Worst Case Algorithm for Reporting Intersections of Rectangles , 1980, IEEE Transactions on Computers.
[8] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[9] Phillip Smtih,et al. The VIVID System Approach to Technology Independence: the Master Technology File System , 1985, 22nd ACM/IEEE Design Automation Conference.
[10] Franco P. Preparata,et al. Finding the Contour of a Union of Iso-Oriented Rectangles , 1980, J. Algorithms.
[11] Chak-Kuen Wong,et al. An algorithm for optimal two-dimensional compaction of VLSI layouts , 1983, Integr..
[12] Jin-fuw Lee,et al. VLSI Layout Compaction with Grid and Mixed Constraints , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Peter W. Cook. Constraint Solver for Generalized IC Layout , 1984, IBM J. Res. Dev..
[14] Ron Y. Pinter,et al. Optimal Chaining of CMOS Transistors in a Functional Cell , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.