A new framework of design rules for compaction of VLSI layouts

A general framework for describing design rules is provided that encompasses space rules, size rules, extension rules, conditional rules, nonpositive rules, and minimum-type and maximum-type rules. Conditional rules considered include topological rules, width rules, and length rules. A fast compaction scheme was developed to handle this variety of rules in an efficient and uniform way. A compactor based on this approach was constructed that can handle several IBM technologies. In one CMOS technology, there are two width rules and two dozen topological rules, in addition to a hundred or so simple rules. The runtime performance data for several design examples, obtained on an IBM 3090 machine, are presented. It is noted that the use of conditional rules increases the computation cost only slightly, while it saves a significant amount of cell area compared with using all simple rules. >

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