A low-power, multichannel gated oscillator-based CDR for short-haul applications

A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18/spl mu/m digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8 V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51 mW/channel/Gbps while occupies 0.045mm/sup 2/ silicon area.

[1]  Yoshiyasu Doi,et al.  A CMOS multi-channel 10-Gb/s Transceiver , 2003 .

[2]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[3]  M. Mizuno,et al.  A 10Gb/s/ch 50mW 120/spl times/130/spl mu/m/sup 2/ clock and data recovery circuit , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[4]  Behzad Razavi.  A Versatile Clock Recovery Architecture and Monolithic Implementation , 1996 .

[5]  Eric Naviasky,et al.  A 62.5 Gb/s multi-standard SerDes IC , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[6]  Behzad Razavi.  Design of intergrated circuits for optical communications , 2002 .

[7]  M. Soda,et al.  A 100 Gb/s transceiver with GND-VDD common-mode receiver and flexible multi-channel aligner , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  Y. Akazawa,et al.  A 156 Mbps CMOS clock recovery circuit for burst-mode transmission , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[9]  Deog-Kyoon Jeong,et al.  Multi-gigabit-rate clock and data recovery based on blind oversampling , 2003, IEEE Commun. Mag..

[10]  Y. Leblebici,et al.  Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[11]  John McNeill,et al.  Jitter in ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.