Micro-architecture design and control speculation for energy reduction

Conventional wisdom states that the best way to design an energy-efficient microprocessor is to design it for high performance, since a high performance processor will complete a task quicker than an energy-conscious design. However, our research group has found ways to reduce energy without impacting performance by controlling the amount of speculation used by the processor in its quest for performance.

[1]  Mark Horowitz,et al.  Energy dissipation in general purpose microprocessors , 1996, IEEE J. Solid State Circuits.

[2]  Eric Rotenberg,et al.  Assigning confidence to conditional branch predictions , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

[3]  Dirk Grunwald,et al.  Selective eager execution on the PolyPath architecture , 1998, ISCA.

[4]  Mark Horowitz,et al.  Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.

[5]  Dirk Grunwald,et al.  Confidence estimation for speculation control , 1998, ISCA.

[6]  Dirk Grunwald,et al.  A Comparison of Two Architectural Power Models , 2000, PACS.

[7]  William H. Mangione-Smith,et al.  The filter cache: an energy efficient memory structure , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[8]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  Mikko H. Lipasti Value locality and speculative execution , 1998 .

[10]  Antonio González,et al.  Energy-effective issue logic , 2001, ISCA 2001.

[11]  Uming Ko,et al.  Energy optimization of multi-level processor cache architectures , 1995, ISLPED '95.

[12]  Mark C. Johnson,et al.  Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[13]  Dirk Grunwald,et al.  Pipeline gating: speculation control for energy reduction , 1998, ISCA.

[14]  Anantha P. Chandrakasan,et al.  Low-Power CMOS Design , 1997 .

[15]  Dirk Grunwald,et al.  Branch prediction using selective branch inversion , 1999, 1999 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00425).

[16]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[17]  Mani B. Srivastava,et al.  Predictive system shutdown and other architectural techniques for energy efficient programmable computation , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[18]  K. Yelick,et al.  The Energy Efficiency Of Iram Architectures , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[19]  W. Robert Daasch,et al.  TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator , 2000, PACS.

[20]  Alvin M. Despain,et al.  Cache design trade-offs for power and performance optimization: a case study , 1995, ISLPED '95.