A Monolithic 10 Gb/s Clock and Data Recovery Circuit

A design of a monolithic IC with clock recovery, data decision and 1:4 demultiplexer for fiber communication of SDH STM-64 implemented in JAZZ 0.18 um CMOS technology is described. A half-rate linear phase detector, a charge pump, a two-pole passive low pass filter, a voltage-controlled oscillator and a demultiplexer build up the clock and data recovery circuit. The stimulate result exhibits 4 ps peak-to-peak jitter for recovered clock and 8 ps peak-to-peak jitter for demultiplexed data respectively with 10 Gb/s pseudo random bit sequence (PSBS). Under 1.8-V supply, the power dissipation is 190 mw.

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