Dynamic logic styles with improved noise-immunity

Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. Noise effects in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE (Balamurugan and Shanbhag, IEEE J. Solid-State Circ., vol. 36, no. 2, pp. 273-280, 2001) by 3.4/spl times/ and 2.8/spl times/ over conventional dynamic true single-phase-clock (TSPC) and Domino logic, respectively. The improvement in the ANTE-delay quotient is 2.8/spl times/ and 2.25/spl times/ over conventional dynamic logic, 2.0/spl times/ and 1.7/spl times/ over twin-transistor technique, 1.7/spl times/ and 1.04/spl times/ over Bobba's technique for CMOS TSPC and Domino AND gates, respectively.

[1]  Naresh R. Shanbhag,et al.  Noise-tolerant dynamic circuit design , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  Kenneth L. Shepard,et al.  Conquering Noise in Deep-Submicron Digital ICs , 1998, IEEE Des. Test Comput..

[3]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Naresh R. Shanbhag,et al.  The twin-transistor noise-tolerant dynamic circuit technique , 2001, IEEE J. Solid State Circuits.

[5]  K. L. Shepard,et al.  Noise in deep submicron digital design , 1996, ICCAD 1996.

[6]  G.A. Katopis,et al.  Delta-I noise specification for a high-performance computing machine , 1985, Proceedings of the IEEE.

[7]  Christer Svensson,et al.  Noise in digital dynamic CMOS circuits , 1994 .

[8]  Ashutosh Das,et al.  A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors , 1999 .

[9]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[10]  Ibrahim N. Hajj,et al.  Design of dynamic circuits with enhanced noise tolerance , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).