A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously. In addition, the on-chip interconnection fabric is extremely high hardware cost for the distributed trace signals. In this paper, we propose a clustering-based scheme which implements concurrent trace for debugging Network-on-Chip (NoC) based multicore systems. In the proposed scheme, a unified communication framework eliminates the requirement for interconnection fabric which is only used during debugging. With clustering scheme, multiple concurrent trace sources can access distributed trace buffer via NoC under bandwidth constraint. We evaluate the proposed scheme using Booksim and the results show the effectiveness of the proposed scheme.

[1]  Kees G. W. Goossens,et al.  Interactive Debug of SoCs with Multiple Clocks , 2011, IEEE Design & Test of Computers.

[2]  Nicola Nicolici,et al.  Low Cost Debug Architecture using Lossy Compression for Silicon Debug , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[3]  Sandip Kundu,et al.  On-Chip Support for NoC-Based SoC Debugging , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Miron Abramovici,et al.  In-System Silicon Validation and Debug , 2008, IEEE Design & Test of Computers.

[5]  Eli Singerman,et al.  Transaction based pre-to-post silicon validation , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[6]  Qiang Xu,et al.  Interconnection fabric design for tracing signals in post-silicon validation , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[7]  Nicola Nicolici,et al.  On Using Lossy Compression for Repeatable Experiments during Silicon Debug , 2011, IEEE Transactions on Computers.

[8]  Qiang Xu,et al.  A Multi-Core Debug Platform for NoC-Based Systems , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[9]  Sriram R. Vangal,et al.  A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.

[10]  Nur A. Touba,et al.  Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[11]  Nicola Nicolici,et al.  Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation , 2008, 2008 Design, Automation and Test in Europe.

[12]  Nagib Hakim,et al.  Post-silicon validation challenges: How EDA and academia can help , 2010, Design Automation Conference.

[13]  Yu-Chin Hsu.  Maximizing Full-Chip Simulation Signal Visibility for Efficient Debug , 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).