A CMOS Low Noise, Chopper Stabilized Low-Dropout Regulator With Current-Mode Feedback Error Amplifier

Low 1/f noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator (LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and 1/f noise accumulation at the chopping frequency, a first-order digital SigmaDelta noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 nV/radic(Hz) and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced 1/f noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 mus settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 mum CMOS process with five layers of metal, occupying 0.88 mm2.

[1]  C. B. Wang A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme , 2001 .

[2]  E. Vittoz,et al.  A CMOS Chopper Amplifier , 1986, ESSCIRC '86: Twelfth European Solid-State Circuits Conference.

[3]  Bram Nauta,et al.  Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology , 1998, IEEE J. Solid State Circuits.

[4]  José Silva-Martínez,et al.  A frequency compensation scheme for LDO voltage regulators , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Wouter A. Serdijn,et al.  Low-power current-mode 0.9-V voltage regulator , 1994 .

[6]  P. Larsson Power supply noise in future IC's: a crystal ball reading , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[7]  Gaetano Palumbo,et al.  CMOS current amplifiers , 1999 .

[8]  J.H. Huijsing,et al.  A CMOS chopper opamp with integrated low-pass filter , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[9]  K. Yeo,et al.  Effect of technology scaling on the 1/f noise of deep submicron PMOS transistors , 2004 .

[10]  J. Choma,et al.  A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter , 2001, IEEE J. Solid State Circuits.

[11]  T. Karnik,et al.  Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[12]  Siew Kuok Hoon,et al.  A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier , 2006, IEEE Custom Integrated Circuits Conference 2006.

[13]  Siew Kuok Hoon,et al.  A CMOS Low-Noise, Low-Dropout Regulator for Transceiver SOC Supply Management , 2006, 2006 IEEE International SOC Conference.

[14]  Franco Maloberti,et al.  A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[15]  Gabriel A. Rincon-Mora,et al.  A low-voltage, low quiescent current, low drop-out regulator , 1998, IEEE J. Solid State Circuits.

[16]  K. Leung,et al.  A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation , 2003, IEEE J. Solid State Circuits.