A probabilistic approach to automatic verification of concurrent systems

The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory.

[1]  David L. Dill,et al.  Better verification through symmetry , 1996, Formal Methods Syst. Des..

[2]  Christos H. Papadimitriou,et al.  On the Random Walk Method for Protocol Testing , 1994, CAV.

[3]  David Notkin,et al.  Model checking large software specifications , 1996, SIGSOFT '96.

[4]  R. Brayton,et al.  High performance BDD package by exploiting memory hierarchy , 1996, 33rd Design Automation Conference Proceedings, 1996.

[5]  Gerard J. Holzmann,et al.  The Model Checker SPIN , 1997, IEEE Trans. Software Eng..

[6]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[7]  Forrest Brewer,et al.  Implementation of an efficient parallel BDD package , 1996, DAC '96.

[8]  David L. Dill,et al.  A New Scheme for Memory-Efficient Probabilistic Verification , 1996, FORTE.

[9]  Gerard J. Holzmann,et al.  The SPIN Model Checker , 2003 .

[10]  R. Bryant Graph-Based Algorithms for Boolean Function Manipulation12 , 1986 .

[11]  Enrico Tronci Hardware verification, Boolean logic programming, Boolean functional programming , 1995, Proceedings of Tenth Annual IEEE Symposium on Logic in Computer Science.

[12]  Alan J. Hu,et al.  Protocol verification as a hardware design aid , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[13]  Enrico Tronci,et al.  Exploiting Transition Locality in Automatic Verification , 2001, CHARME.

[14]  Gerard J. Holzmann,et al.  An Analysis of Bitstate Hashing , 1995, Formal Methods Syst. Des..

[15]  U. Stern,et al.  Using Magnatic Disk Instead of Main Memory in the Murphi Verifier , 1998, CAV.

[16]  Alan J. Hu,et al.  New Techniques for Efficient Verification with Implicitly Conjoined BDDs , 1994, 31st Design Automation Conference.

[17]  Gerard J. Holzmann,et al.  State Compression in SPIN: Recursive Indexing and Compression Training Runs , 2002 .

[18]  Joanne M. Atlee,et al.  State-Based Model Checking of Event-Driven System Requirements , 1993, IEEE Trans. Software Eng..

[19]  David L. Dill,et al.  Parallelizing the Murphi Verifier , 1997, CAV.

[20]  Edmund M. Clarke,et al.  Formal Methods: State of the Art and Future Directions Working Group Members , 1996 .

[21]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[22]  Robert K. Brayton,et al.  Binary decision diagrams on network of workstations , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[23]  Thierry Jéron,et al.  Test Generation Derived from Model-Checking , 1999, CAV.

[24]  Daniel Jackson,et al.  Elements of style: analyzing a software design feature with a counterexample detector , 1996, ISSTA '96.

[25]  Gerard J. Holzmann,et al.  Automating software feature verification , 2000, Bell Labs Technical Journal.

[26]  Myla Archer,et al.  Using Abstraction and Model Checking to Detect Safety Violations in Requirements Specifications , 1998, IEEE Trans. Software Eng..

[27]  Pierre Wolper,et al.  Reliable Hashing without Collosion Detection , 1993, CAV.

[28]  Sérgio Vale Aguiar Campos,et al.  Symbolic Model Checking , 1993, CAV.

[29]  David L. Dill,et al.  Improved probabilistic verification by hash compaction , 1995, CHARME.

[30]  Pao-Ann Hsiung,et al.  Verification of concurrent client-server real-time scheduling systems , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).

[31]  Rajeev Motwani,et al.  Randomized algorithms , 1996, CSUR.

[32]  David L. Dill,et al.  Efficient verification of symmetric concurrent systems , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[33]  Pierre Wolper,et al.  Memory-efficient algorithms for the verification of temporal properties , 1990, Formal Methods Syst. Des..

[34]  Benedetto Intrigila,et al.  Exploiting Transition Lo ality in Automati Veri ation ? , 2001 .