A novel CORDIC-based array architecture for the multidimensional discrete Hartley transform

In this paper, a coordinate rotation digital computer (CORDIC)-based array architecture is presented for computing the multidimensional (M-D) discrete Hartley transform (DHT). Since the kernel of the M-D DHT is inseparable, the M-D DHT problems cannot be computed through the 1-D DHT's directly. Bracewell et al. have presented an algorithm for the M-D DHT through the 1-D DHT's. The existing hardware architectures have been designed using this algorithm. However, the postprocessing required in the algorithm leads to high hardware overhead. This paper presents a new algorithm to compute M-D DHT through a special 1-D transform which is derived through considering both the separable computation and the efficient implementation with CORDIC architectures. This algorithm provides a direct way to compute the M-D DHT separably through 1-D transforms with simpler postprocessing than that in Bracewell's approach. Also, the algorithm exploits the symmetry of the triangular functions to reduce the computational complexity. Using this algorithm, we design an array architecture for the M-D DHT. This architecture features a systolic computing style, PE's with a CORDIC structure, low I/O cost, and the encapsulated new M-D DHT algorithm. >

[1]  Chaitali Chakrabarti,et al.  Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition , 1990, IEEE Trans. Computers.

[2]  Heinrich Meyr,et al.  VLSI implementation of the CORDIC algorithm using redundant arithmetic , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[3]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition , 1989, IEEE Trans. Acoust. Speech Signal Process..

[4]  Chein-Wei Jen,et al.  On the design of VLSI arrays for discrete Fourier transform , 1992 .

[5]  Yu Hen Hu.  A Forward Angle Recoding CORDIC Algorithm and Pipelined Processor Array Structure for Digital Signal Processing , 1993 .

[6]  R. Bracewell,et al.  Fast two-dimensional Hartley transform , 1986, Proceedings of the IEEE.

[7]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[8]  C.-W. Jen,et al.  The design of a systolic array with tags input , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[9]  Anindya Sundar Dhar,et al.  An array architecture for fast computation of discrete Hartley transform , 1991 .

[10]  W. Steenaart,et al.  Efficient one-dimensional systolic array realization of the discrete Fourier transform , 1989 .

[11]  R. Bracewell.  Discrete Hartley transform , 1983 .

[12]  J. S. Walther,et al.  A unified algorithm for elementary functions , 1899, AFIPS '71 (Spring).

[13]  Bedrich J. Hosticka,et al.  Modified CORDIC algorithm with reduced iterations , 1989 .

[14]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[15]  Long-Wen Chang,et al.  Systolic arrays for the discrete Hartley transform , 1991, IEEE Trans. Signal Process..

[16]  Francesco Piazza,et al.  A systolic circuit for fast Hartley transform , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[17]  R. Bracewell.  The fast Hartley transform , 1984, Proceedings of the IEEE.

[18]  Thompson.  Fourier Transforms in VLSI , 1983, IEEE Transactions on Computers.

[19]  Y.H. Hu,et al.  CORDIC-based VLSI architectures for digital signal processing , 1992, IEEE Signal Processing Magazine.

[20]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[21]  Dan E. Dudgeon,et al.  Multidimensional Digital Signal Processing , 1983 .