Low-power design for full adder circuits

Based on studying and analyzing published full adders, a pass transistor based low-power full adder was proposed. The circuit structure of the proposed full adder is symmetrical and the circuit delay is balanced, so glitches are cut down, which leads to power consumption reduction. Using the parameters of TSMC 0.24 μm CMOS device, the low power full adder designed was simulated by PSPICE. The simulation results showed that the power savings of the proposed adder was improved up to 58.3% and 60.8% at 3.3 V supply voltages and 1.8 V supply voltages, respectively, as compared with the published adders.