Self-timed 1-D ICT processor

This paper describes a LSI implementation of 1-D order-8 integer cosine transform (ICT) which can calculate either forward or reverse transformation. It is a standard-cell based design using 0.7 /spl mu/m CMOS SLP DLM process. The chip's performance is maximized with the fast computation algorithm and self-timed circuit technique. It consists of eight parallel self-timed pipelines. Each self-timed block is designed based on 2-phase handshaking protocol and variable delay concept. The die size is 5.7/spl times/4.1 mm with about 76 K transistors. This chip supports 16-bit I/O data and its data rate is up to 60 MHz.