Extraction and Analysis of Interface States in 50-nm nand Flash Devices

A method to extract the interface states (<i>N</i><sub>it</sub>) located in the center area (center <i>N</i><sub>it</sub>) and the <i>N</i><sub>it</sub> located in the corner region (corner <i>N</i><sub>it</sub>) of NAND Flash devices is presented in this paper. This <i>N</i><sub>it</sub> extraction method is based on a careful combination of charge-pumping current data, technology computer-aided-design simulation results, and the “control gate (CG)-modulated corner effect,” where “CG-modulated corner effect” refers to the fact that the electron density in the corner region of the transistor is greatly affected by the bias applied to CG. Using this <i>N</i><sub>it</sub> extraction method, the amounts of center <i>N</i><sub>it</sub> and corner <i>N</i><sub>it</sub> of a given NAND Flash device can be analyzed. In addition, among devices with various widths of active area, the narrower width device showing worse corner <i>N</i><sub>it</sub> can be demonstrated. Furthermore, the generation of center <i>N</i><sub>it</sub> and corner <i>N</i><sub>it</sub> for a device under program/erase cycle stress is explored. Our <i>N</i><sub>it</sub> extraction method will be useful to analyze not only the characteristics of fresh NAND Flash devices but also the reliability of aged NAND Flash devices.

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