A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector. >

[1]  H. Ichino,et al.  Super self-aligned process technology (SST) and its applications , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[2]  K. Sakuma,et al.  A New Self‐Aligned Planar Oxidation Technology , 1987 .

[3]  Y. Amemiya,et al.  A 20 ps/G Si Bipolar IC Using Advanced SST with Collector Ion Implantation , 1987 .

[4]  K. Nakazato,et al.  A 48ps ECL in a self-aligned bipolar technology , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  S. Konaka,et al.  A 30-ps Si bipolar IC using super self-aligned process technology , 1986, IEEE Transactions on Electron Devices.

[6]  Hee K. Park,et al.  High-Speed Self-Aligned Polysilicon Emitter/Base Bipolar Devices Using Boron and Arsenic Diffusion Through Polysilicon , 1986 .

[7]  Ching-Te Chuang,et al.  73ps si bipolar ECL circuits , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  M. Suzuki,et al.  Prospects of SST technology for high speed LSI , 1985, 1985 International Electron Devices Meeting.

[9]  A. E. Michel,et al.  Channeling in low energy boron ion implantation , 1984 .

[10]  Tadashi Sakai,et al.  Gigabit logic bipolar technology: advanced super self-aligned process technology , 1983 .

[11]  C. T. Kirk,et al.  A theory of transistor cutoff frequency (fT) falloff at high current densities , 1962, IRE Transactions on Electron Devices.