ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current

Modified designs of the low-voltage triggering semiconductor-controlled rectifier (LVTSCR) devices with high trigger current are proposed to protect the CMOS output buffer against electrostatic discharge (ESD) events in submicrometer CMOS technologies. The high trigger current is achieved by inserting the bypass diodes into the structures of the modified PMOS-trigger lateral SCR (PTLSCR) and NMOS-trigger lateral SCR (NTLSCR) devices, these modified PTLSCR and NTLSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the accidental triggering due to the electrical noise on the output pad in the normal operating conditions of CMOS IC's. Experimental results have verified that the trigger current of the modified PTLSCR (NTLSCR) is increased up to 225.5 mA (218.5 mA). The noise margin to the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the modified NTLSCR (PTLSCR), is more than VDD+12 V (VSS-12 V).

[1]  Chung-Yu Wu,et al.  Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation , 1995 .

[2]  R. N. Rountree.  ESD protection for submicron CMOS circuits-issues and solutions , 1988, Technical Digest., International Electron Devices Meeting.

[3]  C. Duvvury,et al.  ESD Phenomena and Protection Issues in CMOS Output Buffers , 1987, 25th International Reliability Physics Symposium.

[4]  C. Duvvury,et al.  ESD Protection Reliability in 1μM CMOS Technologies , 1986, 24th International Reliability Physics Symposium.

[5]  Charvaka Duvvury,et al.  A synthesis of ESD input protection scheme , 1992 .

[6]  C. Duvvury,et al.  ESD: a pervasive reliability concern for IC technologies , 1993 .

[7]  Chung-Yu Wu,et al.  Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation , 1995 .

[8]  T. Polgreen,et al.  A low-voltage triggering SCR for on-chip ESD protection at output and input pads , 1990, IEEE Electron Device Letters.

[9]  Chung-Yu Wu,et al.  Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI , 1996 .

[10]  Chung-Yu Wu,et al.  Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's , 1995 .

[11]  Chung-Yu Wu,et al.  A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI , 1992 .

[12]  C. Duvvury,et al.  The impact of technology scaling on ESD robustness and protection circuit design , 1995 .

[13]  Ming-Dou Ker,et al.  Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC , 1995, Proceedings of Eighth International Application Specific Integrated Circuits Conference.