A novel multiplexer-based low-power full adder

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.

[1]  Yuke Wang,et al.  Design and analysis of 10-transistor full adders using novel XOR-XNOR gates , 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

[2]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[3]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[4]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[5]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[6]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .