Through-wafer interconnection by deep damascene process for MEMS and 3D wafer level packaging
暂无分享,去创建一个
N. Balasubramanian | Jiang Ning | C.S. Premachandran | C. Premachandran | N. Balasubramanian | N. Ranganathan | K. Prasad | L. Ebin | Liao Ebin | J. Ning | N. Ranganathan | K. Prasad
[1] A. Fan,et al. Copper Wafer Bonding , 1999 .
[2] J. Burghartz,et al. A micromachining post-process module with pattern transfer in deep cavities for RF silicon technology , 2001, Technical Digest. MEMS 2001. 14th IEEE International Conference on Micro Electro Mechanical Systems (Cat. No.01CH37090).
[3] C. S. Premachandran,et al. A novel electrically conductive wafer through hole filled vias interconnect for 3D MEMS packaging , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..
[4] Cheng-Kok Koh,et al. Power trends and performance characterization of 3-dimensional integration for future technology generations , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.
[5] James D. Meindl,et al. Interconnect Opportunities for Gigascale Integration , 2002, IEEE Micro.
[6] N. Balasubramanian,et al. High Aspect Ratio Through-Wafer Interconnect for Three Dimensional Integrated Circuits , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..
[7] S. Das,et al. Fabrication technologies for three-dimensional integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.
[8] C.C. Liu,et al. Crosstalk attenuation with ground plane structures in three-dimensionally integrated mixed signal systems , 2005, IEEE MTT-S International Microwave Symposium Digest, 2005..
[9] J. Joyner,et al. Opportunities for reduced power dissipation using three-dimensional integration , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).