A novel self-aligned highly reliable sidewall split-gate flash memory

A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F/sup 2/ (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 10/sup 5/ confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250/spl deg/C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.

[1]  Huinan Guan,et al.  An analytical model for optimization of programming efficiency and uniformity of split gate source-side injection SuperFlash memory , 2003 .

[2]  Dirk Wellekens,et al.  A 5V - compatible Flash EEPROM Cell with Microsecond Programming for Embedded Memory Applications , 1994 .

[3]  J. V. Houdt,et al.  Write/erase degradation in source side injection flash EEPROM's: characterization techniques and wearout mechanisms , 1995 .

[4]  T. Ma,et al.  Analysis of enhanced hot-carrier effects in scaled flash memory devices , 1998 .

[5]  T. Chan,et al.  A novel high-speed, 5-volt programming EPROM structure with source-side injection , 1986, 1986 International Electron Devices Meeting.

[6]  Guido Groeseneken,et al.  HIM0S-a high efficiency flash E/sup 2/PROM cell for embedded memory applications , 1993 .

[7]  G. Groeseneken,et al.  A quantitative model for the conduction in oxides thermally grown from polycrystalline silicon , 1986, IEEE Transactions on Electron Devices.

[8]  C.S. Wang,et al.  The impacts of control gate voltage on the cycling endurance of split gate flash memory , 2000, IEEE Electron Device Letters.

[9]  K. Suh,et al.  Data retention failure in NOR flash memory cells , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[10]  Cheng-Yuan Hsu,et al.  Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[11]  Caleb Yu-Sheng Cho,et al.  Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells , 2004 .

[12]  Guido Groeseneken,et al.  An analytical model for the optimization of source-side injection flash EEPROM devices , 1995 .

[13]  Paolo Cappelletti.  Flash memory reliability , 1998 .

[14]  Dana Lee,et al.  A novel 3 volts-only, small sector erase, high density flash E/sup 2/PROM , 1994, Proceedings of 1994 VLSI Technology Symposium.

[15]  Rino Micheloni,et al.  Memory Architecture and Related Issues , 1999 .

[16]  S. C. Tsao,et al.  A novel high density contactless flash memory array using split-gate sources-side-injection cell for 5 V-only applications , 1994, Proceedings of 1994 VLSI Technology Symposium.

[17]  Shinji Taguchi,et al.  A new flash-erase EEPROM cell with a sidewall select-gate on its source side , 1989, International Technical Digest on Electron Devices Meeting.