Challenges and design choices in nanoscale CMOS

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

[1]  J. Burr,et al.  CMOS technology scaling for low voltage low power applications , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[2]  D. Muller,et al.  The electronic structure at the atomic scale of ultrathin gate oxides , 1999, Nature.

[3]  Dimitri Antoniadis,et al.  Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[4]  Yukihito Oowaki,et al.  Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's , 1998 .

[5]  Suman Datta,et al.  Silicon nano-transistors for logic applications , 2003 .

[6]  S. Narendra,et al.  Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[7]  Keith M. Jackson,et al.  Optimal MOSFET design for low temperature operation , 2001 .

[8]  Shan X. Wang,et al.  High frequency (GHz) and low resistance integrated inductors using magnetic materials , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[9]  Masashi Horiguchi,et al.  Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's , 1993 .

[10]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[11]  M. Aoki,et al.  Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs) , 1993 .

[12]  J. Tschanz,et al.  A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[13]  Nasser A. Kurd,et al.  A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.

[14]  Sheng-Chih Lin,et al.  A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management , 2003, IEEE International Electron Devices Meeting 2003.

[15]  G. Ono,et al.  A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[16]  K. Mori,et al.  A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[17]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[18]  Andrew R. Brown,et al.  Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study , 2001 .

[19]  Madhav P. Desai,et al.  The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance , 2002 .

[20]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[21]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[22]  Quantized phonon spectrum of single-wall carbon nanotubes , 2000, Science.

[23]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[24]  R. Mahnkopf,et al.  CMOS with active well bias for low-power and RF/analog applications , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[25]  Rick Smolan,et al.  One Digital Day: How the Microchip is Changing Our World , 1998 .

[26]  Jong-Ho Lee,et al.  Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[27]  Anantha Chandrakasan,et al.  MTCMOS hierarchical sizing based on mutual exclusive discharge patterns , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[28]  Mark C. Johnson,et al.  Design and optimization of dual-threshold circuits for low-voltage low-power applications , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[29]  Takeshi Sakata,et al.  Subthreshold-current reduction circuits for multi-gigabit DRAM's , 1994 .

[30]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[31]  Eby G. Friedman,et al.  Efficiency analysis of a high frequency buck converter for on–chip integration with a dual–V DD microprocessor , 2002 .

[32]  U. Ghoshal,et al.  Refrigeration technologies for sub-ambient temperature operation of computing systems , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[33]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[34]  Masayuki Miyazaki,et al.  A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs , 1998, ISLPED '98.

[35]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.

[36]  A. Taylor,et al.  An on-chip voltage regulator using switched decoupling capacitors , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[37]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[38]  Vivek De,et al.  A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[39]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[40]  P. Larsson.  Power supply noise in future IC's: a crystal ball reading , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[41]  J. Kavalieros,et al.  High-/spl kappa//metal-gate stack and its MOSFET characteristics , 2004, IEEE Electron Device Letters.

[42]  J.D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[43]  Suman Datta,et al.  High- /Metal-Gate Stack and Its MOSFET Characteristics , 2004 .

[44]  藤田 哲也,et al.  A 0.9V 150MHz 10mW 4mm^2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme , 1996 .

[45]  D. Antoniadis,et al.  Physics and technology of ultra short channel MOSFET devices , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[46]  C. Mead,et al.  Fundamental limitations in microelectronics—I. MOS technology , 1972 .

[47]  H. C. Poon,et al.  DC Model for short-channel IGFET's , 1973 .

[48]  S. Thompson.  MOS Scaling: Transistor Challenges for the 21st Century , 1998 .

[49]  G.E. Moore,et al.  No exponential is forever: but "Forever" can be delayed! [semiconductor industry] , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[50]  S. Narendra,et al.  Forward body bias for microprocessors in 130nm technology generation and beyond , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[51]  I. Aller,et al.  CMOS circuit technology for sub-ambient temperature operation , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[52]  Anantha Chandrakasan,et al.  Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[53]  J. Tschanz,et al.  Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[54]  Vivek De,et al.  Monolithic DC-DC converter analysis and MOSFET gate voltage optimization , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[55]  H. Takahashi,et al.  A 1 V DSP for wireless communications , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[56]  Vivek De,et al.  Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED '01.

[57]  K. Kempf.  Improving Throughput Across the Factory Life-Cycle , 2022 .

[58]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[59]  M. Schulz.  The end of the road for silicon? , 1999, Nature.

[60]  Kazuo Yano,et al.  TP 13.3 Threshold Canceling Logic (TCL): A Post-CMOS Logic Family Scalable Down to 0.02∝m , 2000 .

[61]  S. Borkar,et al.  Dynamic-sleep transistor and body bias for active leakage power control of microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[62]  Vivek De,et al.  Cascode buffer for monolithic voltage conversion operating at high input supply voltages , 2005, 2005 IEEE International Symposium on Circuits and Systems.