On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults

This paper proposes a very efficient method to diagnosis multiple bridging faults. This method is based on differential or Delta I/sub DDQ/ probabilistic signatures, as well as on the Viterbi algorithm, mainly used in telecommunications systems for error correction. The proposed method can be seen as a significant improvement over an existing one based on maximum likelihood estimation. The use of the (adapted) Viterbi algorithm allows us to take into account additional information not considered previously. The existing and the proposed method are first described. Then, simulation and experimental results are presented to validate the concept in the context of double faults. Bounds on false diagnosis probability are also provided, estimating the number of test/diagnosis vectors required to reach a given diagnosis reliability for a given number of gates. The bounds allow us to show that this probability exponentially decreases with the number of test vectors and that for, a given value of this probability, the number of vectors required is O(log2(G)), where G is the number of gates.

[1]  C.F. Hawkins,et al.  Identifying defects in deep-submicron CMOS ICs , 1996, IEEE Spectrum.

[2]  Atul Patel,et al.  Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[3]  Claude Thibeault Increasing current testing resolution , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[4]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[5]  Robert C. Aitken Modeling the Unmodelable: Algorithmic Fault Diagnosis , 1997, IEEE Des. Test Comput..

[6]  Kenneth M. Butler,et al.  On applying non-classical defect models to automated diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Irith Pomeranz,et al.  A diagnostic test generation procedure for synchronous sequential circuits based on test elimination , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[8]  Claude Thibeault On the Comparison of IDDQ and IDDQ Testing , 1999, VTS.

[9]  Hiroshi Takahashi,et al.  Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing , 1995, Proceedings of the Fourth Asian Test Symposium.

[10]  Tracy Larrabee,et al.  Probabilistic mixed-model fault diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[11]  Eugene R. Hnatek,et al.  Diagnosing IC Failures in a Fast Environment , 1997, IEEE Des. Test Comput..

[12]  Anjali Kinra,et al.  Diagnostic techniques for the UltraSPARC/sup TM/ microprocessors , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[13]  K. Yeager,et al.  Deep Sub-micron Design , 1996, IEEE Design & Test of Computers.

[14]  J. Soden,et al.  IC failure analysis: techniques and tools for quality reliability improvement , 1993, Proc. IEEE.

[15]  Masahiro Fujita,et al.  Modeling the unknown! Towards model-independent fault and error diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[16]  Israel Koren,et al.  Defect tolerance in VLSI circuits: techniques and yield analysis , 1998, Proc. IEEE.

[17]  David L. Landis,et al.  A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs , 1996, Proceedings of 14th VLSI Test Symposium.

[18]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[19]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[20]  Robert C. Aitken,et al.  Diagnosis of leakage faults with IDDQ , 1992, J. Electron. Test..

[21]  Claude Thibeault,et al.  Can the current behavior of faulty and fault-free ICs and the impact on diagnosis , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[22]  Sreejit Chakravarty,et al.  Algorithms for IDDQ measurement based diagnosis of bridging faults , 1992, J. Electron. Test..

[23]  Wojciech Maly,et al.  Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.

[24]  J. Figueras,et al.  I/sub DDQ/ test and diagnosis of CMOS circuits , 1995 .

[25]  David P. Vallett IC Failure Analysis: The Importance of Test and Diagnostics , 1997, IEEE Des. Test Comput..

[26]  Claude Thibeault,et al.  Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[27]  Kenneth M. Butler,et al.  Automated Diagnosis in Testing and Failure Analysis , 1997, IEEE Des. Test Comput..

[28]  Wojciech Maly,et al.  Current signatures: application , 1997, Proceedings International Test Conference 1997.

[29]  Robert C. Aitken,et al.  Fault Location with Current Monitoring , 1991, 1991, Proceedings. International Test Conference.

[30]  Sheldon M. Ross Introduction to Probability Models. , 1995 .

[31]  Sheldon M. Ross,et al.  Introduction to Probability Models, Eighth Edition , 1972 .

[32]  Richard E. Anderson,et al.  IC Failure Analysis: Magic, Mystery, and Science , 1997, IEEE Des. Test Comput..

[33]  Franco Motika,et al.  Application and analysis of IDDQ diagnostic software , 1997, Proceedings International Test Conference 1997.

[34]  P. Nigh,et al.  An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[35]  Claude Thibeault,et al.  A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[36]  Sandeep K. Gupta,et al.  A new path-oriented effect-cause methodology to diagnose delay failures , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[37]  Weitong Chuang,et al.  Circuit-level dictionaries of CMOS bridging faults , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..