Design and analysis of efficient multilevel receiver for current mode interconnect system

The focus of the present research is to design a receiver circuit for high speed and high throughput data transmission over the interconnect line. This is achieved using current mode signaling in interconnects. In the present paper an efficient receiver for current mode interconnect system is proposed. The analysis shows that the proposed receiver has 26.65% lesser latency at room temperature for an interconnect length of 8 mm and 18.59% at 40°C. It offers higher throughput of 37.5% for an interconnect length of 8mm in comparison to voltage mode interconnect system. The proposed technique shall be useful for systems with operating frequencies in GHz range and low latency requirement.

[1]  Rajeevan Chandel,et al.  Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications , 2012, J. Low Power Electron..

[2]  Hannu Tenhunen,et al.  Modeling of Energy Dissipation in RLC Current-Mode Signaling , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  A. K. Mal,et al.  An explicit approach for bandwidth evaluation of on-chip VLSI RC interconnects with current mode signaling technique , 2010, 2010 Second International conference on Computing, Communication and Networking Technologies.

[4]  Maryam Shojaei Baghini,et al.  A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Alan C. Thomas,et al.  Level-specific lithography optimization for 1-Gb DRAM , 2000 .

[6]  Nasser Masoumi,et al.  Performance improvement of global interconnects using combined techniques of low swing transceiver and buffer insertion in nano technologies , 2011, ICM 2011 Proceeding.

[7]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[8]  Kang Sung-Mo.  CMOS digital integrated circuits: analysis and design / Sung-Mo (Steve) Kang, Yusuf Leblebici , 2003 .

[9]  K. W. Current,et al.  CMOS current comparator circuit , 1983 .

[10]  Shyh-Chyi Wong,et al.  Modeling of interconnect capacitance, delay, and crosstalk in VLSI , 2000 .

[11]  Sung-Mo Kang,et al.  CMOS digital integrated circuits , 1995 .

[12]  Hai Zhou,et al.  Simultaneous routing and buffer insertion with restrictions on buffer locations , 1999, DAC '99.

[13]  M. Khalil-Hani,et al.  s.RABILA2: An optimal VLSI routing algorithm with buffer insertion using iterative RLC model , 2012, 2012 IEEE International Conference on Circuits and Systems (ICCAS).

[14]  Rajeevan Chandel,et al.  An analysis of interconnect delay minimization by low-voltage repeater insertion , 2007, Microelectron. J..

[15]  Sandeep Saini,et al.  An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects , 2010, 2010 23rd International Conference on VLSI Design.

[16]  Dinesh Sharma,et al.  A novel low power multilevel current mode interconnect system , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).