Handheld System Energy Reduction by OS-Driven Refresh

Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy of memory system, which unlike others, lowers energy of refresh operation in DRAM. The approach is based on two key ideas: (1) DRAM-based flash cache that keeps dirty pages to reduce the number of accesses to flash memory; and (2) OS-controlled page allocation/aging to stop the refresh operations in banks, whose pages are clean and not accessed for a long time. Simulations show that by using this technique we can decrease the overall energy consumption of DRAM/flash memory on video applications by 8-26% while reducing the DRAM refresh energy by 59-74%.

[1]  Wonyong Sung,et al.  Compressed Swapping for NAND Flash Memory Based Embedded Systems , 2005, SAMOS.

[2]  Alvin R. Lebeck,et al.  Power aware page allocation , 2000, SIGP.

[3]  Doug Burger,et al.  Evaluating Future Microprocessors: the SimpleScalar Tool Set , 1996 .

[4]  Kang G. Shin,et al.  Design and Implementation of Power-Aware Virtual Memory , 2003, USENIX ATC, General Track.

[5]  Chanik Park,et al.  Energy-aware demand paging on NAND flash-based embedded storages , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[6]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[7]  T. Iwasaki,et al.  A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[8]  Kazuaki Murakami,et al.  Optimizing the DRAM refresh count for merged DRAM/logic LSIs , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[9]  T. Takayanagi,et al.  A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM , 2000, IEEE Journal of Solid-State Circuits.

[10]  Mahmut T. Kandemir,et al.  Scheduler-based DRAM energy management , 2002, DAC '02.

[11]  K. Ohmori,et al.  A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[12]  Naehyuck Chang,et al.  Low-Energy Heterogeneous Non-Volatile Memory Systems for Mobile Systems , 2005, J. Low Power Electron..

[13]  Kang G. Shin,et al.  Improving energy efficiency by making DRAM less randomly accessed , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[14]  Carla Schlatter Ellis,et al.  Memory controller policies for DRAM power management , 2001, ISLPED '01.