Accurate parasitic resistance extraction for interconnection analysis

With the further scaling down of feature sizes, parasitic resistance is becoming more important for interconnection analysis. Previous resistance modeling and extraction methods either sacrifice too much speed for accuracy or sacrifice too much accuracy for speed. Neither of which is sufficient for effective interconnection analysis. In this paper we present a parasitic resistance extraction methodology which is both fast and accurate. The strategy is to fracture the resistive polygons into regions of different electromagnetic complexity and then use different algorithms to solve each region of complexity. Experimental results show that extracted resistances are within 5% of pure FEM resistance extraction for most test cases and within 10% for a few extreme cases while performing the extraction only about an order of magnitude slower than the path-finding parasitic resistance extraction technique.

[1]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[2]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluator , 1991, 28th ACM/IEEE Design Automation Conference.

[3]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Rainer Leupers,et al.  Resistance Extraction Using a Routing Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[5]  M. Harbour,et al.  Calculation of multiterminal resistances in integrated circuits , 1986 .

[6]  Kenji Yoshida,et al.  A Resistance Calculation Algorithm and Its Application to Circuit Extraction , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.