Mixed-signal programmable non-linear interface for resource-efficient multi-sensor analytics

Tremendous progress has been made in reducing ADC power-consumption, yet, in many portable always-awake and multi-sensor systems, the power consumption is dominated by digital backend processing [1] for feature-computation and classification. Recent Analog-to-Information based innovations (see Fig. 21.1.1) have attempted to alleviate this bottleneck by reducing the amount of data streaming into the digital domain: (a) by extracting sensory features in the analog domain [2] and digitizing these instead of the raw-data; and (b) by compressing the data through an analog non-linearity in order to reduce the required digitization word-length [3-5]. Yet, both approaches suffer from limited applicability and design reuse problems, due to (a) their need for highly application-specific building blocks which are not portable across different sensor-signals in multi-sensor platforms; and (b) their need for complex, performance-sensitive analog building blocks which are not portable across silicon technologies. Overcoming the above shortcomings, this work reports a highly programmable non-linear interface that synergistically combines a digitally-computed, application-tunable non-linearity with a 10b binary DAC in an iterative mixed-signal loop (see Fig. 21.1.1 bottom) to enable a compressive analog to non-linear digital transfer-curve. Such configurable non-linear transfer-curve has wide applicability in multi-sensor analytics for feature-extraction, signal-emphasis/-de-emphasis, signal-correction, etc. A 90nm CMOS proof-of-concept illustrates this versatility with 2 very different application mappings, demonstrating (a) Compressive classification: 2x improvement in rms-error for heart-beat classification from muscle noise corrupted ECG signals, along with 50% backend data reduction; and (b) Analog impairment correction : up-to 20dB distortion correction for analog impairments in the sensory chain.

[1]  Marian Verhelst,et al.  24.2 Context-aware hierarchical information-sensing in a 6μW 90nm CMOS voice activity detector , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Anantha P. Chandrakasan,et al.  18.2 A fully-implantable cochlear implant SoC with piezoelectric middle-ear sensor and energy-efficient stimulation in 0.18μm HVCMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[3]  Amir M. Sodagar,et al.  Nonlinear Signal-Specific ADC for Efficient Neural Recording in Brain-Machine Interfaces , 2014, IEEE Transactions on Biomedical Circuits and Systems.

[4]  Jongwoo Lee,et al.  A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC , 2009, IEEE Journal of Solid-State Circuits.

[5]  R. Sarpeshkar,et al.  A micropower logarithmic A/D with offset and temperature compensation , 2004, IEEE Journal of Solid-State Circuits.