On-chip Parametric Test of R-2R Ladder Digital-to-Analog Converter and Its Efficiency

This paper deals with the investigation of the fault detection in separated parts of a mixed-signal integrated circuit example by implementing parametric test methods. The experimental Circuit Under Test (CUT) consisting of an 8-bit binaryweighted R-2R ladder digital-to-analog converter and additional on-chip test hardware was designed in a standard 0.35μm CMOS technology. For detection of catastrophic and parametric faults considered in different parts of the CUT, two dedicated parametric test methods: oscillation-based test technique and IDDQ monitoring were used. For the operational amplifier, onchip and off-chip approaches have been used to compare the efficiency of both approaches in covering catastrophic faults that are hard to detect. For respective converter parts, the excelent fault coverage of 94.21% of hard-detectable faults by the proposed parametric tests was achieved.

[1]  José Luis Huertas,et al.  New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters , 2001, J. Electron. Test..

[2]  Karim Arabi,et al.  A New Built-in Self-test Approach For Digital-to-analog And Analog-to-digital Converters , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[3]  Kwang-Ting Cheng,et al.  A BIST scheme for on-chip ADC and DAC testing , 2000, DATE '00.

[4]  José L. Huertas.  Test and Design-for-Testability in Mixed-Signal Integrated Circuits , 2004 .

[5]  Hanjun Jiang,et al.  High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy , 2009, IEEE Transactions on Instrumentation and Measurement.

[6]  Bozena Kaminska,et al.  BIST for D/A and A/D Converters , 1996, IEEE Des. Test Comput..

[7]  R. Rajsuman,et al.  Iddq testing for CMOS VLSI , 1994, Proceedings of the IEEE.

[8]  Bozena Kaminska,et al.  Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits , 1997, Proceedings International Test Conference 1997.

[9]  Joan Figueras,et al.  Characterization of Floating Gate Defects in Analog Cells , 1999, J. Electron. Test..

[10]  B. Kaminska,et al.  Oscillation-test strategy for analog and mixed-signal integrated circuits , 1996, Proceedings of 14th VLSI Test Symposium.

[11]  Tsin-Yuan Chang,et al.  An embedded built-in-self-test approach for digital-to-analog converters , 2001, Proceedings 10th Asian Test Symposium.

[12]  Viera Stopjaková,et al.  CCII+ current conveyor based BIC monitor for I/sub DDQ/ testing of complex CMOS circuits , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[13]  Karim Arabi,et al.  Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[14]  Chun Wei Lin,et al.  A BIST scheme for testing DAC , 2012, 2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology.

[15]  K. Gunavathi,et al.  A novel on chip circuit for fault detection in digital to analog converters , 2009, 2009 International Conference on Control, Automation, Communication and Energy Conservation.

[16]  Karim Arabi,et al.  Mixed Signal DFT: A Concise Overview , 2003, ICCAD.

[17]  Pasquale Daponte,et al.  IEEE Std.1658 - IEEE Standard for Terminology and Test Methods of Digital-to-Analog Converter Devices , 2012 .

[18]  Chun Wei Lin,et al.  A new approach for nonlinearity test of high speed DAC , 2008, 2008 IEEE 14th International Mixed-Signals, Sensors, and Systems Test Workshop.

[19]  Kaushik Roy,et al.  A high performance IDDQ testable cache for scaled CMOS technologies , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[20]  Mohamad Sawan,et al.  On chip testing data converters using static parameters , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[21]  Gloria Huertas Sanchez,et al.  Oscillation-Based Test in Mixed-Signal Circuits (Frontiers in Electronic Testing) , 2006 .

[22]  Chien-In Henry Chen,et al.  Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters , 2007, IEEE Transactions on Instrumentation and Measurement.

[23]  R. Rajsuman.  Design-for-Iddq-testing for embedded cores based system-on-a-chip , 1998, Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232).

[24]  Tachibana Masayoshi,et al.  A BIST scheme based on resistance match for current-mode R-2R ladder Digital-to-Analog Converter , 2011, 2011 3rd International Conference on Computer Research and Development.

[25]  Narumi Sakashita,et al.  A built-in self-test for ADC and DAC in a single-chip speech CODEC , 1993, Proceedings of IEEE International Test Conference - (ITC).

[26]  Daniel Arbet,et al.  Increasing the efficiency of analog OBIST using on-chip compensation of technology variations , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.