Synthesis of ASIPs for DSP algorithms

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific integrated processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.

[1]  Gert Goossens,et al.  Embedded software in real-time signal processing systems: application and architecture trends , 1997 .

[2]  Allen Dewey,et al.  VHDL Motivation , 1986, IEEE Design & Test of Computers.

[3]  Sang-Sik Ahn,et al.  Convergence of the DLMS algorithm with decreasing step size , 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

[4]  Catherine H. Gebotys,et al.  Synthesizing Embedded Speed-optimized Architectures , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[5]  P. Six,et al.  Cathedral-II: A Silicon Compiler for Digital Signal Processing , 1986, IEEE Design & Test of Computers.

[6]  S. K. Nandy,et al.  Synthesis of configurable architectures for DSP algorithms , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[7]  Fuyun Ling,et al.  The LMS algorithm with delayed coefficient adaptation , 1989, IEEE Trans. Acoust. Speech Signal Process..

[8]  Keshab K. Parhi,et al.  High-level algorithm and architecture transformations for DSP synthesis , 1995, J. VLSI Signal Process..

[9]  Keshab K. Parhi,et al.  High level DSP synthesis using the MARS design system , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[10]  A. W. M. van den Enden,et al.  Discrete Time Signal Processing , 1989 .

[11]  Gert Goossens,et al.  Embedded software in real-time signal processing systems: design technologies , 1997, Proc. IEEE.

[12]  Charles E. Leiserson,et al.  Optimizing synchronous systems , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[13]  Mohamed I. Elmasry,et al.  Architectural synthesis for DSP silicon compilers , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Catherine H. Gebotys,et al.  Optimal synthesis of high-performance architectures , 1992 .

[15]  Visvanathan,et al.  Synthesis of energy-efficient configurable processor arrays , 1994 .

[16]  Anantha Chandrakasan,et al.  Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[17]  S. K. Nandy,et al.  Architectural Synthesis of Computational Engines for Subband Adaptive Filtering , 1999, J. VLSI Signal Process..

[18]  S. Ramanathan,et al.  Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1 , 1999, Integr..

[19]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[20]  Albert E. Casavant,et al.  Scheduling and hardware sharing in pipelined data paths , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[21]  August Kaelin,et al.  Analysis of the LMS algorithm with delayed coefficient update , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[22]  Mohamed I. Elmasry,et al.  Global optimization approach for architectural synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  V. von Kaenel,et al.  A voltage reduction technique for battery-operated systems , 1990 .

[25]  S. K. Nandy,et al.  Architectural Synthesis of Low-Power Computational Engines for LMS Adaptive Filtering , 1998 .

[26]  G. Goossens,et al.  Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment , 1991 .

[27]  Keshab K. Parhi,et al.  Synthesis of control circuits in folded pipelined DSP architectures , 1992 .

[28]  Mani B. Srivastava,et al.  Predictive system shutdown and other architectural techniques for energy efficient programmable computation , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[29]  Hugo De Man,et al.  Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications , 1996, DAC '96.