A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.

[1]  P. Garrou,et al.  Wafer level chip scale packaging (WL-CSP): an overview , 2000, ECTC 2000.

[2]  R. Chanchani,et al.  mini Ball Grid Array (mBGA) assembly on MCM-L boards , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.

[3]  Shu-Ming Chang,et al.  Investigation of electroplating Ni UBM for Pb-free solders , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[4]  Thomas A. Wassick,et al.  Evaluation of Cu capping alternatives for polyimide-Cu MCM-D , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[5]  I. Anjoh,et al.  Development of low-cost and highly reliable wafer process package , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[6]  Shu-Ming Chang,et al.  The development of enhanced wafer level packaging , 2002, 4th Electronics Packaging Technology Conference, 2002..

[7]  Muhannad S. Bakir,et al.  Sea of leads ultra high-density compliant wafer-level packaging technology , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[8]  John H. Lau,et al.  Chip scale package (CSP) : design, materials, processes, reliability, and applications , 1999 .

[9]  Eiichi Kondoh,et al.  Material characterization of Cu(Ti)-polyimide thin film stacks , 2000 .

[10]  E. Beyne,et al.  Integration of a low stress photopatternable silicone into a wafer level package , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[11]  Rajen Chanchani,et al.  A new mini Ball Grid Array (mBGA) multichip module technology , 1994 .

[12]  P.S. Ho,et al.  Interfacial adhesion study for copper/SiLK interconnects in flip-chip packages , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[13]  Wei Koh.  Memory device packaging - from leadframe packages to wafer level packages , 2004, Proceedings of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP '04).

[14]  S. Pozder,et al.  Analysis of flip-chip packaging challenges on copper/low-k interconnects , 2003 .

[15]  John H. Lau,et al.  A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints , 2000, Packaging of Electronic and Photonic Devices.