Performance-Driven Clustering of Asynchronous Circuits

This paper proposes the method of generating asynchronous circuits from hardware description language specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput and latency constraints, and minimizing area. This method provides a form of automatic pipelining in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original Register-Transfer Level (RTL) specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles.

[1]  Mitchell A. Thornton,et al.  A fine-grain Phased Logic CPU , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[2]  Luciano Lavagno,et al.  From synchronous to asynchronous: an automatic approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Scott A. Brandt,et al.  NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[4]  Peter A. Beerel,et al.  Performance-Driven Clustering of Asynchronous Circuits , 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Jianhua Li,et al.  A connectivity based clustering algorithm with application to VLSI circuit partitioning , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Peter A. Beerel,et al.  A Designer's Guide to Asynchronous VLSI , 2010 .

[7]  Marly Roncken,et al.  The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..

[8]  Ivan E. Sutherland,et al.  GasP: a minimal FIFO control , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[9]  Piyush Prakash,et al.  Slack matching quasi delay-insensitive circuits , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[10]  K. Meekins,et al.  Delay insensitive NCL reconfigurable logic , 2002, Proceedings, IEEE Aerospace Conference.

[11]  Seth Copen Goldstein,et al.  Operation chaining asynchronous pipelined circuits , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[12]  Andrew B. Kahng,et al.  Multilevel circuit partitioning , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Peter A. Beerel,et al.  Proteus: An ASIC Flow for GHz Asynchronous Designs , 2011, IEEE Design & Test of Computers.

[14]  Ross Smith,et al.  Asynchronous design using commercial HDL synthesis tools , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[15]  Mitchell A. Thornton,et al.  A Coarse-Grain Phased Logic CPU , 2005, IEEE Trans. Computers.

[16]  Luciano Lavagno,et al.  Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Alex Kondratyev,et al.  Design of asynchronous circuits by synchronous CAD tools , 2002, DAC '02.

[18]  Alex Kondratyev,et al.  Design of Asynchronous Circuits Using Synchronous CAD Tools , 2002, IEEE Des. Test Comput..

[19]  Mark G. Karpovsky,et al.  An automated fine-grain pipelining using domino style asynchronous library , 2005, Fifth International Conference on Application of Concurrency to System Design (ACSD'05).

[20]  Stephen Longfield,et al.  A Low Power Asynchronous GPS Baseband Processor , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

[21]  Pankaj Golani,et al.  An area-efficient multi-level single-track pipeline template , 2011, 2011 Design, Automation & Test in Europe.

[22]  Peter A. Beerel,et al.  Slack matching asynchronous designs , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[23]  Steven M. Nowick,et al.  High-Performance Asynchronous Pipelines: An Overview , 2011, IEEE Design & Test of Computers.

[24]  Vishal Gupta,et al.  Performance estimation and slack matching for pipelined asynchronous architectures with choice , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.