A fully parallel CMOS analog median filter

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The array median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on transconductance comparators to speed their time response, while the time delay is implemented using all-pass filters. Both circuits allow modular expansion for the implementation of large sized median filter array processors. In addition, a fast novel technique for parallel image processing is presented. It is shown that an image of 91/spl times/81 pixels is processed in less than 30 /spl mu/S using an array of high-speed analog processors. Experimental results of a test chip prototype in 2 /spl mu/m CMOS technology MOSIS process are presented.

[1]  B I Justusson,et al.  Median Filtering: Statistical Properties , 1981 .

[2]  Bin-Da Liu,et al.  Design and implementation of an analogue median filter for real-time processing , 1993 .

[3]  K. T. Lau,et al.  MOS circuits for median filtering applications , 1993 .

[4]  Gregory T. A. Kovacs,et al.  A high-speed median circuit , 1997 .

[5]  L. R. Carley,et al.  An analog circuit technique for finding the median , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[6]  Dana S. Richards,et al.  VLSI median filters , 1990, IEEE Trans. Acoust. Speech Signal Process..

[7]  Ioannis Pitas,et al.  Nonlinear Digital Filters - Principles and Applications , 1990, The Springer International Series in Engineering and Computer Science.