SJ-LDMOS with high breakdown voltage and ultra-low on-resistance

A new design concept is proposed to eliminate the substrate-assisted depletion effect in a super-junction (SJ) LDMOS. The key feature of the concept is that a non-uniform N-buried layer is implemented which compensates for the charge interaction between the P-substrate and SJ region, realising high breakdown voltage (>700 V) and ultra-low on-resistance. Furthermore, the proposed device is compatible with smart power technology.

[1]  S. Hardikar,et al.  Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping , 2004, IEEE Transactions on Electron Devices.

[2]  A.W. Ludikhuize.  A versatile 250/300-V IC process for analog and switching applications , 1986, IEEE Transactions on Electron Devices.

[3]  Bo Zhang,et al.  A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC , 2006, Microelectron. J..

[4]  S.G. Nassif-Khalil,et al.  SJ/RESURF LDMOST , 2004, IEEE Transactions on Electron Devices.

[5]  C.A.T. Salama,et al.  Super-junction LDMOST on a silicon-on-sapphire substrate , 2003 .

[6]  Florin Udrea,et al.  Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI , 2001, Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).

[7]  S. Merchant,et al.  Arbitrary lateral diffusion profiles , 1995 .

[8]  Wanjun Chen,et al.  Design and Optimization of a Versatile 700 V SPIC Process Using a Fully Implanted Triple-well Technology , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[9]  C.A.T. Salama,et al.  Optimization of RESURF LDMOS transistors: an analytical approach , 1990 .