Investigation of durability of TSV interconnect by numerical thermal fatigue analysis

Abstract3D packaging using through silicon via (TSV) technology is becoming important in IC packaging industry. However, increased number of interconnects and extreme miniaturization suggest that thermo-mechanical reliability and fatigue will aggravate. In traditional package, thermo-mechanical fatigue failure mostly occurs as a result of damage in the solder joint. In TSV technology, however, the driving failure may be the TSV via or TSV interconnects. In this study, the durability of TSV technology is investigated using finite element method. Thermal fatigue phenomenon due to the plastic strain caused by repetitive temperature cycling is analyzed, and possible failure locations are discussed. In particular, the effects of via size, underfill material, and via filling material on the thermal fatigue reliability are investigated. The expected fatigue life indicates that the presence of underfill material is essential in improving the durability of the TSV structure. The plastic strain increases with the via size increases, therefore the thermal fatigue life increases as the via size decreases. For different via filling materials such as copper, nickel and tungsten, amount of plastic strain is very similar, suggesting that nickel could be used for via filling material. However, the locations of the maximum strain are different for each filling material.

[1]  M. Gad-el-Hak The MEMS Handbook , 2001 .

[2]  Dae-Gon Kim,et al.  Evaluation of solder joint reliability in flip chip package under thermal shock test , 2006 .

[3]  Xiaowu Zhang,et al.  Development of 3-D Silicon Module With TSV for System in Packaging , 2010, IEEE Transactions on Components and Packaging Technologies.

[4]  Zhaowei Zhong,et al.  Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA , 2006, Microelectron. Reliab..

[5]  V. Moroz,et al.  Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV) , 2009, 2009 IEEE International Reliability Physics Symposium.

[6]  Jian-Qiang Lu,et al.  Modeling Thermal Stresses in 3-D IC Interwafer Interconnects , 2006, IEEE Transactions on Semiconductor Manufacturing.

[7]  R. Tummala,et al.  Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV) , 2009, 2009 59th Electronic Components and Technology Conference.

[8]  Helene Fremont,et al.  Design for reliability: Thermo-mechanical analyses of stress in Through Silicon Via , 2010, 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE).

[9]  V. Lee,et al.  Development of 3D silicon module with TSV for system in packaging , 2008, 2008 58th Electronic Components and Technology Conference.

[10]  Leila Ladani,et al.  Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits , 2010 .

[11]  Hsien-Chie Cheng,et al.  Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection , 2010, Microelectron. Reliab..

[12]  Kyung-Jin Choi,et al.  Analysis of silicon via hole drilling for wafer level chip stacking by UV laser , 2010 .

[13]  K. Vaidyanathan,et al.  Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps , 2008, 2008 58th Electronic Components and Technology Conference.