Hyperelliptic curve crtpto processor hardware apparatus

In an apparatus for a hyperelliptic-curve cryptography processing, an input/output control block controls a peripheral component interconnect (PCI) interface block, a direct memory access (DMA) and a data input/output. An input memory block stores an external instruction and input data provided by the PCI interface block. An output memory block stores a final and an intermediate value of a hyperelliptic-curve cryptography operation. A MUX controls a path of input/output data. An operation core block performs a genus one elliptic-curve and a genus two hyperelliptic-curve cryptography algorithm, respectively. A controlling device controls the operation core block.